1. Field of the Invention
The present invention relates to a CMOS logic circuit comprising on the same substrate p-channel and n-channel MOS transistors in a logic circuit configuration and, more particularly, to an analog-digital hybrid IC device comprising a CMOS logic circuit and an analog circuit on the same substrate.
2. Description of Related Art
Digital computers can be built using only digital circuitry, but multimedia information systems and human interface systems in which graphic and audio information is dealt with must be able to handle not only digital signals, but also analog signals. This has made it necessary to construct devices using both analog circuits and digital circuits.
In a conventional CMOS logic circuit, an applied input signal causes a transistor or other circuit element to become either conducting or non-conducting to produce a particular output signal. During this operation, charging and discharging the parasitic electrostatic capacitance of the circuit causes a transient current to be drawn from the power source and flow out through the ground. As this transient current flows through resistance and impedance elements on the power supply line, it produces a switching noise. This switching noise occurs particularly in digital circuits and, in a typical analog-digital hybrid IC device as shown in FIG. 1, leaks from the digital circuit to the analog circuit side through wiring and the IC substrate. This noise has a limiting effect on the dynamic range and S/N ratio of the analog circuit. It is therefore not possible to achieve a high precision analog circuit.
The mechanism whereby noise is generated in a CMOS logic circuit will be discussed with reference to an inverter shown in FIG. 2. It should be noted that the operation of any common CMOS gate can be generally described with reference to the inverter.
A typical IC device normally has a sheet resistance of 50 m.OMEGA./.mu.m2 on the power supply and ground lines. For example, a line, 10 .mu.m wide and 1 mm long, has a 5 .OMEGA. sheet resistance. In the example shown in FIG. 2, Rps and RG are wiring resistances on the power supply and ground lines. The wiring capacitance and input gate capacitance of the next element are also connected to the output of each gate as load capacitance CL. FIG. 2 is a model circuit diagram of this arrangement. When a pulse is applied to this circuit, a charge/discharge current flows to CL. When the charge current flows, ground line resistance RG produces a voltage boost at a node Q in FIG. 2. This results in an up spike in the ground potential as shown in FIG. 3. A charge current likewise produces a down spike in the line potential at a node P.
In a typical n-well CMOS IC device, switching noise is inserted to the p-substrate because node Q is an NMOS source and is connected to the substrate. In a typical IC, the substrates are used in common by the digital circuit and analog circuit parts, which are thus electrically connected, and are therefore a major factor in the leakage of switching noise from the digital part to the analog circuit part. Furthermore, if the power supply and ground lines are also shared with the analog circuit part, the aluminum lines are another factor in switching noise leakage to the analog circuit part.
One method known in the art for reducing noise in a CMOS logic circuit is to use wiring lines to connect substrate contacts as shown in FIG. 4. Referring to FIG. 4 which illustrates a typical circuit diagram for this configuration, there are two power supply and ground lines in this case; one for circuit drive and one for connection to the substrate. Unlike in the conventional CMOS logic circuit, the circuit is not connected to the substrate at the node Q, and noise at the node Q is therefore not inserted to the substrate. Substrate noise does occur in this device as described below.
As indicated by the dotted lines in FIG. 4, parasitic capacitances Cgb (between the gate and substrate) and Cdb (between the drain and substrate) are present at the MOS transistors. If we consider the paths from a node I to the ground GND2 through a node X and from the junction O to the ground GND2 through the node X in FIG. 4, an RC differential circuit is formed and the potential at the node I (input) or O (output) varies considerably according to the input/output pulse. This produces a differential waveform, which appears as substrate noise, at the node X (p-substrate). This noise is normally amplified by parasitic impedance and oscillates (FIG. 16 (b)).
Current steering logic (CSL) circuits are known in the art as basic logic circuits suitable for noise reduction. The CSL circuits, however, do not use CMOS logic circuits in the form as they are and, instead, require that the logic circuit be designed as a CSL circuit and, in this sense, these types of the CSL circuits are not directly related to the intent of the present invention. (See, for example, David J. Allstot et al., "Analog Logic Techniques Steering Around the Noise", IEEE Circuits & Devices, Vol. 9, No. 9, September 1993, pp. 18-21.)